About Me
I'm a current coterm (BS + MS student) studying Electrical Engineering at Stanford University. I am excited about developing power-efficient hardware accelerators for machine learning and other emerging applications.
Erik Luna
eluna1@stanford.edu • (408) 903-8088 • linkedin.com/in/erik-luna/ • www.erikluna.me
Education
Stanford University | Expected: June 2024
M.S. in Electrical Engineering – Hardware/Software track.
B.S. in Electrical Engineering – Hardware/Software track.
Relevant Coursework: VLSI Design Projects I, Intro to VLSI Design, Computer Architecture, Machine Learning, Digital Systems Engineering, Operating Systems, Interconnection Networks, Circuits II, and Signal Processing II.
Technical Skills
Hardware: SystemVerilog, HLS, Cadence Virtuoso, SkyWater 130nm, LTSpice, HSpice, XModel, Vivado.
Software: Python, Java, C++, C, C#, Typescript, Python, Julia, MATLAB, TCL, MIPS assembly, Git.
Experience
Stanford Electrical Engineering Department | Stanford, CA
REU Program Research Assistant | June 2023 – Sept. 2023
Simulated 3D neural network document retrieval accelerator for faster queries in the Brains in Silicon Lab.
Developed Crossbar controller module in Python and Verilog for reads/writes to 3D memory cube.
Estimated power dissipation of chip based on gathered query statistics from the database.
Microsoft | Redmond, WA
Software Engineer Intern | June 2022 – Sept. 2022
React framework web development
Created a command line tool to onboard developers into Azure DevOps’ package manager in C#.
Developed a package migration service into Azure Artifacts from third-party repositories like Artifactory.
Integrated REST API requests using C# libraries to request package information and download.
Program Management and Software Engineer Intern | June 2021 – Sept. 2021
Participated in Explore rotational program as PM and SWE in MS Azure, flagship cloud computing service.
Implemented web portal extension in React for AnyBuild customers (developers) on the Azure marketplace.
Expecting upwards of 10,000 developers within and outside of MS to process builds after public release.
Collected and documented feedback from 15+ Developers, Designers, and Program Managers.
Stanford Electrical Engineering Department | Stanford, CA
REU Program Research Assistant | June 2020 – Sept. 2020
Organized a team of eleven other student researchers in designing a smell communication device.
Analyzed sensory data using Python through principle component analysis and k-means algorithm.
Implemented Kivy GUI to transfer data between Firebase (Google database platform) and WiFi Arduino.
Reproduced 4 smells with over 80% accuracy to the user with software and hardware components.
Personal Project
Society of Latinx Engineers site – sole.stanford.edu | Mar 2020 – June 2020
Developing website using HTML and JavaScript for club’s online visibility and increased engagement.
Updating subscriptions and embedded calendar for the most up-to-date meeting information.
Class Projects
ResNet-18 Neural Network Accelerator | Spring 2023
• Implemented ResNet-18 algorithm in HLS and Verilog across design, synthesis, place and route, and layout. • Optimized HLS and Verilog to minimize the area on the chip while meeting performance specifications.
• Simulated in Cadence Innovus, read waveforms, and edited memory macros with Catapult UI.
Graphics Rasterizer | Winter 2022
• Implemented a rasterizer of graphics vectors to pixels in C++ and SystemVerilog, and performed verification.
• Programmed the implementation in HLS (High Level Synthesis) to compare with RTL performance.
• Placed first out of 30 groups in Field of Merit, a measure of throughput, area, and power minimization.
MIPS Five Staged Pipelined Processor | Winter 2022
• Developed a five-stage pipelined processor in Verilog to process 30+ MIPS assembly instructions in series.
• Resolved dependencies and debugged timing issues for all MIPS instructions and verified using testbenches.
FPGA Music Synthesizer | Fall 2021
• Programmed a music player in Verilog to read sheet music out of ROM and display sinusoids in color.
• Debugged and wrote Verilog testbenches for digital logic.
Leadership
Ritmo De Stanford | Stanford, CA
Financial Officer | Sept 2020 – June 2021
Financial Officer | Sept 2020 – June 2021
Managing budget of $6,500, spending across dance workshops, social events, and outside instructor visits.
Leading 20+ person weekly workshops in Latin bachata dance. Coordinating community dance socials.
Toastmasters International | Stanford, CA
VP of Public Relations | June 2021 – Sept 2021
Delivering speeches and providing constructive feedback to other members to master presentations.
Organizing club meetings for 20+ people, leading marketing for club via three social media platforms.
Stanford Entrepreneurial Students Association | Stanford, CA
Treks Committee | Sept 2020 – June 2021
Coordinated Alumni entrepreneur virtual visits for coffee chats and facilitating 20+ person discussions.
Developed startup idea via a quarter-long workshop; pitched video-communication app to VC investor panel.
Society of Latinx Engineers | Stanford, CA
Media Director | Sept 2019 – June 2021
Leading & regulating mailing lists; managing official website for club updates.
Publishing weekly professional development events via social media; increased social media following by 120%.
Additional Information
Languages: Spanish (fluent)
Interests: Latin Dance, Public Service, Basketball, Weightlifting, Graphic Design.
Honors/Awards: Eagle Scout, Hispanic Scholarship Fund Scholar, Cardinal Bellarmine Award, National AP, Scholar with Recognition, National Hispanic Recognition Award.