About Me

I'm a current coterm (BS + MS student) studying Electrical Engineering at Stanford University. I am excited about developing power-efficient hardware accelerators for machine learning and other emerging applications. 


Erik Luna

eluna1@stanford.edu • (408) 903-8088 • linkedin.com/in/erik-luna/ • www.erikluna.me

Education

Stanford University | Expected: June 2024

Technical Skills

Experience

Stanford Electrical Engineering Department | Stanford, CA 

REU Program Research Assistant | June 2023 – Sept. 2023

Microsoft | Redmond, WA

Software Engineer Intern | June 2022 – Sept. 2022

Program Management and Software Engineer Intern | June 2021 – Sept. 2021

Stanford Electrical Engineering Department | Stanford, CA 

REU Program Research Assistant | June 2020 – Sept. 2020

Personal Project

Society of Latinx Engineers site – sole.stanford.edu | Mar 2020 – June 2020

Class Projects

ResNet-18 Neural Network Accelerator | Spring 2023

• Implemented ResNet-18 algorithm in HLS and Verilog across design, synthesis, place and route, and layout. • Optimized HLS and Verilog to minimize the area on the chip while meeting performance specifications.

• Simulated in Cadence Innovus, read waveforms, and edited memory macros with Catapult UI.

Graphics Rasterizer | Winter 2022 

• Implemented a rasterizer of graphics vectors to pixels in C++ and SystemVerilog, and performed verification.

• Programmed the implementation in HLS (High Level Synthesis) to compare with RTL performance.

• Placed first out of 30 groups in Field of Merit, a measure of throughput, area, and power minimization.

MIPS Five Staged Pipelined Processor | Winter 2022 

• Developed a five-stage pipelined processor in Verilog to process 30+ MIPS assembly instructions in series.

• Resolved dependencies and debugged timing issues for all MIPS instructions and verified using testbenches.

FPGA Music Synthesizer | Fall 2021 

• Programmed a music player in Verilog to read sheet music out of ROM and display sinusoids in color.

• Debugged and wrote Verilog testbenches for digital logic.

Leadership  

Ritmo De Stanford | Stanford, CA
Financial Officer | Sept 2020 – June 2021

Toastmasters International | Stanford, CA 

VP of Public Relations | June 2021 – Sept 2021

Stanford Entrepreneurial Students Association | Stanford, CA

Treks Committee | Sept 2020 – June 2021

Society of Latinx Engineers | Stanford, CA 

Media Director | Sept 2019 – June 2021

Additional Information